Design and Implementation of a Mitchell-based Logarithmic Converter for a Floating Point Coprocessor

This paper presents a method to approach the implementation of a highly accurate logarithmic converter that operates with floating point numbers. For consistency purposes, it was necessary to adopt a standard to represent all floating point number. Hence, the IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754) was the one selected. This logarithmic converter is based on Mitchell’s algorithms approximations. Thus, it was necessary to add an error correction unit to the architecture. Despite of this, the processing speed of this logarithmic converter is not affected. The system implemented reduces the maximum error percent down to 0.541 percent, and performs the binary-to-binary logarithmic conversion using 3 clock cycles.